Beta 21 (RC1):

http://www.winuae.net/files/b/winuae_3100b21.zip

Beta 21: (RC1)

- b17 DSKSYNC update should not have started DMA in WORDSYNC mode.
- Moved A590/A2091 ram autoconfig board after HD board. A2091 install disk RAM tester expects it. (Some other boards may also have wrong HD/Fast RAM board order)
- Debugger deep trainer "not modified" condition fixed.
- AROS ROM updated.
Beta 22 (RC2):

http://www.winuae.net/files/b/winuae_3100b22.zip

Beta 22: (RC2)

- In some rare situatations both "HARD_DDF_STOP" and "plf_passed_stop" test conditions incorrectly passed in single fetch block. Only happened when DDFSTRT/DDFSTOP value pair caused bitplane dma overrun so result was different corrupted display. (Plastic Passion / Upfront plasma part with OCS Agnus)
- BPL DMA pointer modified one cycle before same channel´s BPLxDAT gets accessed behavior adjusted. (Powertrax / The Light Circle)
- Archos ADD-500 is also confirmed having fast ram autoconfig board after HD controller.